The structure of a conventional memory cell is disclosed, for example, in U.S. Pat. No. 5,761,121 directed to a memory cell for a PMOS structure. More specifically, such a cell includes a floating-gate transistor and a control gate which is produced by implantation within a semiconductor substrate. This buried layer, which acts as control gate is capacitively coupled to the floating gate. The control gate and the floating-gate transistor are electrically isolated by an isolation zone, for example of the STI (Shallow Trench Isolation) type. The layer of gate material, generally made of polysilicon, within which the floating gate of the transistor is produced, is isolated from the active zone by a dielectric, for example, silicon dioxide.
Although such a memory cell is programmed by injecting hot electrons into the floating gate of the transistor, these being called CHE (Channel Hot Electrons), such a memory cell is electrically erased by applying a high voltage to the source, the drain and the substrate of the transistor and by applying a much lower voltage to the control gate. This induces a high reverse electric field and therefore causes the electrons stored in the floating gate to be extracted and sent into the source, drain and channel regions of the transistor, and by doing so passing through the gate oxide of the transistor.
However, this erase process, when it is repeated in a cyclic fashion, as is generally the case for memory applications, causes the gate oxide of the transistor and the threshold voltage of this transistor to be degraded. In other words, repeatedly extracting the electrons through the gate oxide of the transistor eventually causes aging of the transistor. This problem needs to be addressed.